Senior Analog Layout Engineer & Methodology Leader
Synopsys Inc
A global semiconductor leader seeks a seasoned engineering leader to advance analog and mixed-signal IP development. You will define methodologies, enhance workflow, and provide technical leadership to ensure high-quality design outcomes. With over 5 years of experience required, candidates should have expertise in analog/mixed-signal layout and familiarity with industry tools like Synopsys Custom Compiler and Cadence Virtuoso. You'll mentor junior engineers while collaborating with interdisciplinary teams to drive innovative solutions in a fast-paced environment. #J-18808-Ljbffr
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