Senior Asic Verification Engineer Soc Interconnect

ASIC verification specialists can shape robust UVM environments for NVIDIA Tegra SoC IP, focusing on complex coherent interconnect and system interfaces.

This Senior Verification Engineer position supports the Tegra SoC IP Verification team and High Speed Coherent Interconnect Hub IP. You will define test plans, develop verification infrastructure, and verify protocol compliance across complex interfaces. Collaboration spans architecture, design, FPGA, emulation, software, and post-silicon teams.

Key Responsibilities:

• Maintain constrained-random verification infrastructure and testbenches
• Complete plans covering protocol compliance and key IP features
• Debug RTL and verification issues with architecture and design teams
• Support system validation and silicon bring-up activities
• Drive functional and code coverage toward signoff

Requirements:

• Three-plus years of complex ASIC verification experience
• Strong SystemVerilog and UVM methodology knowledge
• Experience with constrained-random and coverage-driven verification
• Experience creating checkers, assertions, and functional coverage
• Strong problem-solving skills with simulation and debug tools

Bring ASIC verification, UVM infrastructure, protocol analysis, and cross-functional debugging skills to NVIDIA’s Tegra interconnect programs.

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