ASIC Verification Principal Engineer at Synopsys

Drive innovation in PCIe PHY verification at Synopsys as a principal engineer. This position offers remote opportunities focusing on quality and execution in silicon IP solutions. As a senior verification leader, you will establish strategies for next-generation PCIe PHY IP verification and develop extensive plans addressing functional quality. Collaborating with various teams will ensure thorough cross-functional case coverage throughout your projects. Key Responsibilities:

• Establish verification strategy for PCIe PHY IP performance
• Develop plans emphasizing protocol compliance and functionality
• Execute advanced testbench environments for verification
• Collaborate closely with design and validation teams
• Mentor peers and advance verification best practices

Requirements:

• Extensive background in mixed-signal ASIC verification
• In-depth knowledge of PCIe and SerDes architecture
• Hands-on experience with verification methodologies like UVM
• Strong analytical and problem-solving capabilities
• Excellent communication for global teamwork

Enhance Synopsys' reputation in high-speed silicon IP and deliver reliable solutions. #J-18808-Ljbffr