Physical Design Senior Staff Engineer Needed

Join Infineon's Physical Design team as a Senior Staff Engineer, specializing in timing analysis and constraints for cutting-edge low-power SoCs aimed at the IOT and MCU markets. With at least 8 years of experience, you will take ownership of timing closure processes and develop constraints at the pre/post layout stages. This role involves close collaboration with the physical design team and mentoring less experienced staff in synthesis and equivalence checks. Your expertise will guide the team in overcoming timing/SI closure challenges. Key Responsibilities:

• Manage STA and timing closure for low-power SoCs
• Develop constraints for functional and test modes
• Perform timing analysis across hierarchical designs
• Work with physical design teams to achieve timing closure
• Mentor on synthesis and equivalence checks

Requirements:

• Minimum 8 years in timing closure and constraints development
• Expert in using timing signoff tools
• Proficient in scripting languages like shell, perl, and tcl
• Familiar with 22nm/28nm/40nm technology issues
• Background in low-power synthesis is beneficial

Enhance IOT solutions through your expertise at Infineon. #J-18808-Ljbffr