Asic Dft Implementation Technical Lead

Lead ASIC Design-for-Test implementation for Cisco Silicon One, applying scan insertion, ATPG, and gate-level simulation expertise to networking chips.As an ASIC Implementation Technical Lead, you will work across front-end RTL and backend physical design teams. You will understand chip architecture, drive DFT requirements early, and contribute to next-generation networking chips. The work spans implementation flow, quality processes, post-silicon validation, and selected physical design signoff activities.Key Responsibilities:
Drive DFT requirements with front-end RTL and physical design teamsLead DFT and quality processes through implementation flowSupport post-silicon validation and debug phasesContribute to next-generation networking chip developmentProvide exposure to physical design signoff activitiesRequirements:
Bachelor’s degree and eight-plus years of ASIC Design experienceMaster’s degree and six-plus years of ASIC Design experiencePrior scan insertion and ATPG experience using Tessent tool setsGate-level SDF simulation and VCS debugging experiencePost-silicon validation and ATE pattern translation experienceApply ASIC implementation, DFT, ATPG, and validation expertise to Cisco Silicon One networking silicon development.
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