Dsp - Fec Design Engineer

DSP - FEC Design EngineerCelero Communications Inc. is an exciting and fast-growing start-up in the semiconductor industry, pushing boundaries with innovative technologies that power the world’s most advanced AI and data center infrastructure. We are looking for skilled and motivated engineers to join our team and help us build optical transceivers for next-generation optical modems. The ideal candidate must have a strong theoretical background in coding theory, digital communications, and error correction techniques, with experience developing high-performance forward error correction (FEC) algorithms for high-speed communication systems. Candidates with industry experience are preferred.Key Responsibilities
Research, develop, and evaluate forward error correction (FEC) schemes for high-speed optical communication systems.Design and optimize soft‑decision FEC algorithms suitable for high-throughput optical modem implementations.Develop and evaluate coding schemes such as LDPC, staircase codes, or related high-performance FEC architectures.Model and simulate FEC performance in optical communication systems, including interaction with DSP blocks and channel impairments.Analyze performance trade‑offs including coding gain, latency, throughput, and implementation complexity.Develop floating‑point and fixed‑point simulation models for algorithm verification.Implement bit‑accurate and cycle‑accurate models supporting ASIC implementation.Collaborate closely with DSP, ASIC, firmware, and verification teams to ensure efficient hardware implementation.Document algorithm design and simulation results.Preferred Qualifications
Master’s or Ph.D. degree in Electrical Engineering, Mathematics, Computer Engineering, or related field.Strong background in coding theory and error correction algorithms.Experience with FEC schemes for communication systems, particularly soft‑decision FEC.Familiarity with LDPC, staircase codes, product codes, or related modern FEC techniques.Experience evaluating coding gain, BER performance, and decoder complexity.Programming experience in C/C++, Python, MATLAB, or similar languages.Experience in modeling communication systems.Familiarity with DSP algorithms for communication systems.Experience with version control systems, specifically GitHub.Familiarity with hardware implementation considerations and languages such as Verilog or VHDL is a plus.Team player with a mindset focused on the successful delivery of the first product.CelerocatsoneJavier LeonTalent Acquisition619-227-3193 cell/View email address on ca.hrm.tc
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