Senior Coherent Interconnect Verification Engineer

SystemVerilog and UVM expertise meet NVIDIA’s High Speed Coherent Interconnect Hub verification work in a senior engineering position.As a Senior Verification Engineer, you will support Tegra SoC IP Verification by working with architecture and design teams. You will verify complex interconnect IP through constrained-random and coverage-driven methodologies. The work includes protocol compliance, performance validation, debugging, and design signoff.Key Responsibilities:
Develop testbenches, BFMs, checkers, monitors, scoreboards, and assertionsDefine verification plans for coherency, ordering, errors, and performanceVerify interoperability across SoC and multi-chip interfacesValidate bandwidth, latency, QoS, and traffic requirementsDrive coverage closure and verification signoffRequirements:
BS, MS, or equivalent experienceThree-plus years verifying complex ASIC IPs or SoC subsystemsStrong SystemVerilog, UVM, and constrained-random verification backgroundExperience developing verification environments, checkers, assertions, and coverageStrong debugging skills using industry-standard simulation toolsApply coherent interconnect verification, UVM, debugging, and coverage expertise to NVIDIA’s next-generation computing platforms.
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