Serdes Digital Design Verification Engineer

High speed SerDes verification needs SystemVerilog and UVM expertise at Qualcomm Canada ULC. Help validate connectivity for modern AI data centers.This Senior Verification Engineer supports the HSI Digital Design Verification team, specializing in SerDes technology and reliable high bandwidth communication. You will review specifications, create verification plans, and develop testbenches for digital designs. Responsibilities include analog model integration, MATLAB bit matching, Ethernet and PCIe compliance testing, and simulation debug. The position also involves collaboration across Design, Systems, Firmware, and Analog teams.Key Responsibilities:
Devise verification plans from digital design specificationsBuild testbenches and constrained random test casesFacilitate bit matching between RTL and MATLAB modelsIntegrate VIPs for Ethernet and PCIe compliance testingCollaborate on issues and achieve verification closureRequirements:
Master’s degree and one-plus year of relevant ASIC experienceStrong SystemVerilog and UVM verification environment experienceSerDes, DSP, or mixed signal verification experience preferredExposure to formal, gate level, and UPF verificationStrong communication, planning, and debugging skillsBring SerDes, mixed signal, SystemVerilog, and UVM verification skills to Qualcomm’s connectivity engineering work.
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