Security Design Verification Engineer

Apply SystemVerilog UVM and security verification expertise at Arm, with hybrid working patterns determined by team needs. Help validate security IP for pioneering SoC designs.As a Design Verification Engineer, you will work on cryptography, key management, embedded microprocessor systems, hardware root of trust, and secure boot. You will help define and realize hardware security IP and subsystems. The work spans test planning, testbench development, verification models, test strategies, and productization. You will partner with design teams for functional sign off, comprehensive coverage, and power and performance optimization.Key Responsibilities:
Craft test plans and verification strategies for security IPDevelop UVM, SystemVerilog, Verilog, and C testbenchesDebug test failures and verification issuesPartner with design teams on functional sign offMentor team members and support project initiativesRequirements:
Three-plus years verifying sophisticated IP, subsystems, or SoCsBachelor’s or Master’s degree in a related fieldUnderstanding of Verilog HDL and SystemVerilog UVMExperience with security hardware, cryptography, and secure bootExperience with Python, Perl, Tcl, or similar scriptingBring security hardware, UVM, and embedded verification expertise to Arm’s Hardware Security IP development and SoC programs.
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