Soc Lead Engineer - Lec & Low Power Signoff

ADVANCE YOUR CAREER. ADVANCE THE WORLD.At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future.Whether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger — technology that moves the world forward. Join us and, together, we’ll advance your career.THE ROLE
We are seeking a technical lead with strong ownership to drive Low Power Static Verification and Logical Equivalence Check (LEC) signoff as part of our SoC (System-on-Chip) development efforts, across full-chip and block-level designs. The ideal candidate is a self-driven leader who can take end-to-end ownership, lead and work closely with a small team, and drive tasks to completion with minimal supervision. Leadership capability and technical depth matter more than years of experience.THE PERSON
Lead and own the full LEC signoff chain from RTL to physical netlist (RTL, post-synthesis netlist, post-DFT netlist, post-floorplan netlist, and post-P&R (GDS-level) netlist).Drive full-chip top-level and tile-level low power static checks across all stages of the SoC design flow.Debug and resolve logical equivalence and low power static check issues in synthesis and place-and-route flows.Lead a small team, owning task delivery, milestone tracking, and issue resolution.Guide team members on LEC strategy and track design changes across project phases.Preferred Qualifications
Proven experience in SoC implementation and tapeout.Demonstrated leadership owning and driving LEC and low power static verification to completion.In-depth expertise in Logical Equivalence Check (LEC) and Low Power Static Verification.Strong understanding of and hands-on coding experience in Verilog and VHDL.Hands-on with industry-standard EDA tools:
LEC: Synopsys Formality and/or Cadence ConformalLow Power Static Signoff: Synopsys VC-LP (preferred) or Cadence Conformal Low Power (CLP)Synthesis: Design Compiler / Fusion CompilerStatic Timing Analysis (STA): PrimeTimePlace & Route: IC Compiler II / Fusion Compiler (a plus)
Solid understanding of low power design and UPF-based methodology, including UPF implementation and evolution across Synthesis and Place-and-Route (PnR) flows.Strong scripting skills (Tcl, Perl, Python).Leadership & Ownership – Independently drives and coordinates tasks, working closely with a small team to deliver to completion.Strong problem-solving and debugging skills.Excellent communication, documentation, and teamwork.ACADEMIC CREDENTIALS
BS/MS in Electrical Engineering, ECE, EEE, or related field.Benefits offered are described: AMD benefits at a glance.AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD's "Responsible AI Policy" is available here.This posting is for an existing vacancy.
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