Asic Digital Design, Architect

Note: This position is posted for Markham, but it is open to candidates across Canada, including Mississauga, Nepean, and Ottawa. The role can be hybrid or fully remote depending on your location and preference.
We AreSynopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.
You AreYou have spent a decade or more designing digital logic that has to work at the edge of what silicon can do. High-speed SerDes, clock domain crossings that could sink a tapeout, power budgets measured in milliwatts because every one counts. You know that the hardest part of mixed-signal ASIC design is not the RTL, it is the boundary between digital and analog, where timing meets noise and specifications meet reality. You have debugged gate-level sims at 2 a.M. and found the one async crossing that everyone else missed.
You think in terms of design intent, not just passing checks. When you write Verilog, you are already thinking about what synthesis will do to it, what DFT will need, and how verification will cover it. You do not hand off a block and hope for the best. You sit with the verification team, you walk through the testplan, and you help debug the failures that matter.
Mentorship is not a checkbox for you. You have brought junior engineers along, shown them how to think through a problem instead of just fixing their code. At Synopsys, you will architect digital logic for next-generation Ethernet, PCIe, SATA, and USB PHYs that ship in products around the world. The team is expert-level, the problems are real, and what you design will matter.
What You'll Be DoingArchitect and design digital subsystems for high-speed SerDes IP including Backplane Ethernet, PCIe, SATA, and USB 2/3 PHYsAnalyze and define digital and analog interface specifications, translating system-level requirements into implementable RTL and design constraintsDrive design flow decisions for clock domain crossing, synthesis, DFT insertion, and low-power architecture across complex mixed-signal blocksCollaborate directly with ASIC verification engineers to define testplans, review assertion and code coverage, and close functional coverage gapsPerform gate-level simulation, analyze timing and power, and debug failure cases across digital and mixed-signal boundariesMentor junior design engineers on RTL quality, design intent, synthesis impact, and cross-functional collaborationWork across design groups and customer support teams to resolve design issues, clarify specifications, and support silicon bring-up
The Impact You Will HaveYour architectural decisions will define the performance, power, and area of SerDes IP used in high-volume networking and storage products worldwideThe design flows and methodologies you establish will set the standard for how the team handles CDC, DFT, and low-power design across future product generationsYour collaboration with verification will reduce tapeout risk and catch critical issues before they reach siliconThe testplans and coverage strategies you help create will directly improve functional quality and reduce post-silicon debug cyclesYour mentorship will accelerate the growth of junior engineers and raise the technical bar across the teamThe specifications you write will become the foundation for cross-functional alignment between digital, analog, verification, and implementation teamsYour work will enable customers to deliver faster, lower-power, more reliable connectivity in everything from data centers to consumer devices
What You'll NeedMaster's degree in Electrical Engineering, Computer Engineering, or equivalent practical experience10+ years of hands-on digital ASIC design experience, with significant work in high-speed or mixed-signal environmentsStrong proficiency in Verilog or VHDL for RTL design and gate-level simulationDeep understanding of clock domain crossing design, analysis, and verification methodologiesHands-on experience with synthesis tools and techniques, including timing closure and power optimizationSolid knowledge of DFT methodologies including scan insertion, ATPG, and boundary scanExperience working closely with verification teams on testplan creation, coverage closure, and failure analysis. Familiarity with high-speed digital interfaces such as Ethernet, PCIe, SATA, or USB is a strong plus.
Who You AreYou can look at a block diagram and immediately spot the async crossing that is going to cause problems three months from nowYou write RTL with synthesis in mind, not as an afterthought, and you know how to balance design intent with tool limitationsYou are comfortable sitting with an analog designer to hash out an interface spec, then turning around and explaining the same thing to a verification engineer in a way that makes sense for testbench architectureYou do not wait for perfect documentation. You ask the right questions, fill in the gaps, and move forward without creating downstream confusionYou have strong opinions about code quality, coverage metrics, and design methodology, and you are willing to push back when something does not make senseYou can explain a complex timing or power tradeoff to a senior leader in two sentences without losing the technical nuance
The Team You'll Be Part OfYou will join a highly experienced mixed-signal design team responsible for delivering industry-leading SerDes IP for Backplane Ethernet, PCIe, SATA, and USB standards. This team works across the full design cycle, from early specification development through silicon validation and customer support. Your recruiter will share more about the team structure, current product roadmap, and collaboration model during the interview process.
Rewards and BenefitsWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.
#J-18808-Ljbffr