Salaire moyen: $106 675 /annuel
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- ...FPGA projects, from RTL through synthesis. • RTL design: Fluent Verilog / SystemVerilog: microarchitecture, datapaths, FSMs, pipelines, FIFOs, clock-domain crossings, and clock gating. • Synthesis and PPA: Hands-on logic synthesis with timing constraints. You read timing and...SuggéréСontratPour les contractantsFreelanceTravail à distanceTravail à domicile
$45 - $55 par heure
...indexing, and reading query plans (EXPLAIN ANALYZE). The ORM is TypeORM. ◦ AWS serverless and event-driven design: Lambda, SQS (including FIFO queues and dead-letter queues), SNS, Parameter Store. ◦ API design: REST/OpenAPI with generated typed SDKs for consumers, plus...Fly in fly outСontratTravail à distance